verification history

Asic verification has gone various stages of improvements.Days in verilog where we need to key in each and every scenario by way of writing directed testcases . Verisity came out with coverage driven methodology using e. When writing environment the coding guidelines are left to the freewill of users. Verisity came out with eRM to enable user to write resusable and highly scalable code. In evey product verification takes lot of time and portabilty across project is necessity . When companies are trying to reduce the cycle of product tapeout, these needs to be in minds of every engineer who build verification environment. There are several other languages like Vera and System verilog came in to market. System verilog proposes single language for design and verification. OVM from cadence is helpfull is buidling a verification environment in shorter duration